CMD_PARSE_ERROR=Val_0x0, BUS_STATUS=Val_0x0, WD_FAULT=Val_0x0, ECC_FAULT=Val_0x0, RESET_STATUS=Val_0x0, IRQ_RAISED=Val_0x0, STATE=Val_0x0, PMU_IRQ_RAISED=Val_0x0, FAULTING_INTERFACE=Val_0x0, CMD_END_REACHED=Val_0x0, FAULTING_CHANNEL=Val_0x0
Status Register
| STATE | NPU state. 0 (Val_0x0): Stopped 1 (Val_0x1): Running |
| IRQ_RAISED | Raw IRQ status. 0 (Val_0x0): IRQ not raised 1 (Val_0x1): IRQ raised. Can be cleared via the NPUHE_CMD[CLEAR_IRQ] field. |
| BUS_STATUS | Bus status. 0 (Val_0x0): OK 1 (Val_0x1): Bus abort detected and processing halted (NPU has reached IDLE state and does not start to process any more commands / AXI transactions). Can only be cleared by reset. |
| RESET_STATUS | Reset status. 0 (Val_0x0): NPU is not being reset and can be accessed as normal. 1 (Val_0x1): Reset is ongoing and only this register can be read (other registers read as 0 and writes are ignored). |
| CMD_PARSE_ERROR | Command stream parsing error status. 0 (Val_0x0): No error 1 (Val_0x1): Command stream parsing error detected. Can only be cleared by reset. |
| CMD_END_REACHED | Command stream end status. 0 (Val_0x0): End not reached 1 (Val_0x1): End reached. Can be cleared by writing NPUHE_QBASE0 / NPUHE_QBASE1 or NPUHE_QSIZE when NPU is in stopped state. |
| PMU_IRQ_RAISED | PMU IRQ status. 0 (Val_0x0): PMU IRQ not raised 1 (Val_0x1): PMU IRQ raised. Can be cleared via the NPUHE_CMD[CLEAR_IRQ] field. |
| WD_FAULT | Weight decoder state. Note: This bit is never set in this product. 0 (Val_0x0): No fault 1 (Val_0x1): Weight decoder decompression fault signalled. Can only be cleared by reset. |
| ECC_FAULT | ECC state for internal RAMs. 0 (Val_0x0): No fault 1 (Val_0x1): ECC fault signalled. Can only be cleared by reset. |
| FAULTING_INTERFACE | Faulting interface on bus abort. 0 (Val_0x0): AXI-M0 1 (Val_0x1): AXI-M1 |
| FAULTING_CHANNEL | Faulting channel on a bus abort. Read operations: Write operations: 0 (Val_0x0): Cmd 1 (Val_0x1): IFM 2 (Val_0x2): Weights 3 (Val_0x3): Bias and Scale 4 (Val_0x4): Mem2Mem 8 (Val_0x8): OFM 9 (Val_0x9): Mem2Mem |
| IRQ_HISTORY_MASK | IRQ history mask. This is used for debug purposes. Each IRQ or event operation provides a 16-bit mask which is logically OR-ed into these bits. The bits can be cleared via their counterparts in the NPUHE_CMD[CLEAR_IRQ_HISTORY] field. |